available si91872 vishay siliconix document number: 72013 s-51147?rev. f, 20-jun-05 www.vishay.com 1 300-ma low-noise ldo regulator with error flag and discharge option features ultra low dropout?300 mv at 300-ma load low noise?75 v rms (10-hz to 100-khz) out-of-regulation error flag (power good) shutdown control 130- a ground current at 300-ma load fast start-up (50 s) 1.5% guaranteed output voltage accuracy 400-ma peak output current capability uses low esr ceramic capacitors fast line and load transient response ( 30 s) 1- a maximum shutdown current output current limit reverse battery protection built-in short circuit and thermal protection output?auto-discharge in shutdown mode fixed 1.2, 1.8, 2.5, 2.6, 2.8, 3.0, 3.3, 5.0-v output voltage options mlp33-5 powerpak package applications cellular phones, wireless handsets noise-sensitive electronic systems, laptop and palmtop computers pdas pagers digital cameras mp3 player wireless modem description the si91872 is a 300-ma cmos ldo (low dropout) voltage regulator. it is the perfect choice for low voltage, low power applications. an ultra low ground current and ultra fast turn-on make this part attractive for battery operated power systems. the si91872 also offers ultra low dropout voltage to prolong battery life in portable electronics. systems requiring a quiet voltage source will benefit from the si91872?s low output noise. the si91872 is designed to maintain regulation while delivering 400-ma peak current, making it ideal for systems that have a high surge current upon turn-on. for better transient response and regulation, an active pull-down circuit is built into the si91872 to clamp the output voltage when it rises beyond normal regulation. the si91872 automatically discharges the output voltage by connecting the output to ground through a 100- n-channel mosfet when the device is put in shutdown mode. the si91872 features reverse battery protection to limit reverse current flow to approximately 1- a in the event reversed battery is applied at the input, thus preventing damage to the ic. the si91872 is available in both the standard and lead (pb)-free 5-pin mlp33 powerpak packages and is specified to operate over the industrial temperature range of ? 40 c to 85 . typical application circuit si91872 v in gnd sd v out error v in sd v out 2.2 f 51 k error mlp33-5 2.2 f
si91872 vishay siliconix www.vishay.com 2 document number: 72013 s-51147?rev. f, 20-jun-05 absolute maximum ratings absolute maximum ratings input voltage, v in to gnd ? 6.0 to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v error , v sd (see detailed description) ? 0.3 v to v in . . . . . . . . . . . . . . . . . . output current, i out short circuit protected . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage, v out ? 0.3 v to v in + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . package power dissipation, (p d ) b 2.3 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal resistance ( ja ) a 55 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . r ( ja) a 8 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum junction temperature, t j(max) 150 c . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. device mounted with all leads soldered or welded to pc board. b. derate 20 mw/ c above t a = 25 c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating range input v oltage, v in 2 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v sd 0 v to v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current 0 to 300 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c in , c out a (ceramic) 2.2 f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ambient temperature, t a ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . operating junction temperature, t j ? 40 c to 125 c . . . . . . . . . . . . . . . . . . . notes a. maximum esr of c out: 0.2 specifications test conditions unless specified t a = 25 c , v in = v out(nom) + 1 v , i out = 1 ma , limits ? 40 to 85 c parameter symbol t a = 25 c , v in = v out(nom) + 1 v , i out = 1 ma , c in = 2 f, c out = 2.0 f, v sd = 1.5 v temp a min b typ c max b unit input voltage range v in full 2 6 v v out 18 v room ? 2.0 1 2.0 output voltage accuracy 1 ma i out 300 ma v out 1.8 v full ? 3.0 1 3.0 % output voltage accuracy 1 ma i out 300 ma v out = 1 2 v 1 5 v room ? 2.5 1 2.5 % v out = 1.2 v, 1.5 v full ? 3.5 1 3.5 line regulation (v out 3 v) full ? 0.06 0.18 line regulation (3.0 v < v out 3.6 v) v out 100 v in v out(nom) from v in = v out(nom) + 1 v to v out(nom) + 2 v full 0 0.3 %/v line regulation (5-v v ersion) () from v in = 5.5 v to 6 v full 0 0.4 i out = 1 ma room 1 dt vlt dg i out = 50 ma room 45 80 dropout voltage d, g (v out(nom) 2.6 v) i out = 50 ma full 50 90 (v out(nom) 2 . 6 v) i out = 300 ma room 300 350 v in ? v out i out = 300 ma full 415 mv v in v out i out = 50 ma room 65 100 mv dro p out volta g e d, g i out = 50 ma full 120 dropout voltage d, g (v out(nom) 2.6 v, v in 2 v) i out = 300 ma room 400 520 () i out = 300 ma full 570 i out = 0 ma room 100 150 ground pin current e, g i out = 0 ma full 180 ground pin current e, g (v out(nom) 3 v) i out = 300 ma room 130 200 () i gnd i out = 300 ma full 330 a i gnd i out = 0 ma room 110 170 a ground pin current e, g i out = 0 ma full 200 ground pin current e, g (v out(nom) 3 v) i out = 300 ma room 150 225 () i out = 300 ma full 275 peak output current i o(peak) v out 0.95 x v out(nom) . t pw = 2 ms full 400 ma output noise voltage e n v out = 2.6 v, bw = 10 hz to 100 khz, 0 ma i out 150 ma room 75 v(rms)
si91872 vishay siliconix document number: 72013 s-51147?rev. f, 20-jun-05 www.vishay.com 3 specifications limits ? 40 to 85 c temp a test conditions unless specified t a = 25 c, v in = v out(nom) + 1 v, i out = 1 ma, c in = 2 f, c out = 2.0 f, v sd = 1.5 v parameter unit max b typ c min b temp a test conditions unless specified t a = 25 c, v in = v out(nom) + 1 v, i out = 1 ma, c in = 2 f, c out = 2.0 f, v sd = 1.5 v symbol f = 1 khz room 60 ripple rejection v out / v in i out = 300 ma f = 10 khz room 40 db pp j out in out f = 100 khz room 30 dynamic line regulation v o(line) v in : v out(nom) + 1 v to v out(nom) + 2 v t r /t f = 2 s, i out = 300 ma room 20 mv dynamic load regulation v o(load) i out : 1 ma to 300 ma, t r /t f = 2 s room 25 mv thermal shutdown junction temperature t j(s/d) room 150 c thermal hysteresis t hyst room 20 c reverse current i r v in = ? 6.0 v room 1 a short circuit current i sc v out = 0 v room 700 ma shutdown shutdown supply current i cc(off) v sd = 0 v room 0.1 1 a sd pin input voltage v sd high = regulator on (rising) full 1.5 v in v sd pin input voltage v sd low = regulator off (falling) full 0.4 v auto discharge resistance r_dis si91872 only room 100 sd pin input current f i in(sd ) v sd = 1.5 v, v in = 6 v room 0.7 a sd hysteresis v hyst(sd ) full 150 mv v out turn-on time t on v sd (see figure 1), i load = 100 ma room 50 s error output error high leakage i off error v in . v out in regulation full 1 a error low voltage v ol i sink = 0.5 ma full 0.4 v error volta g e threshold v err o r v out below v out(nom) g , v in 2 v v out falling, i out = 1 ma, v out(nom) 2 v full ? 2 ? 4 ? 6 error voltage threshold v error v out(nom) g 2 v, v in 2 v full ? 4 % error voltage threshold hysteresis v hyst(error ) room 1.5 % notes a. room = 25 c, full = ? 40 to 85 c. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-v differential, provided that v in does not not drop below 2.0 v. e. ground current is specified for normal operation as well as ?drop-out? operation. f. the device?s shutdown pin includes a typical 2-m internal pull-down resistor connected to ground. g. v out(nom) is v out when measured with a 1-v differential to v in . timing waveforms figure 1. timing diagram for power-up v sd 0.95 v nom v out v nom t on 0 v v in t r 1 s
si91872 vishay siliconix www.vishay.com 4 document number: 72013 s-51147?rev. f, 20-jun-05 pin configuration: mlp33-5 mlp33-5 powerpak 1 2 1 2 3 4 5 3 4 5 sd error v in v out gnd gnd gnd gnd top view bottom view pin description pin number name function 1 sd by applying less than 0.4 v to this pin, the device will be turned off. connect this pin to v in if unused 2 error the open drain output is an error flag output which goes low when v out drops 4% below its nominal voltage. 3 v in input supply pin. bypass this pin with a 1- f ceramic or tantalum capacitor to ground 4 v out output voltage. connect c out between this pin and ground. 5 gnd ground pin. for better thermal capability, directly connected to large ground plane ordering information standard part number lead (pb)-free part number marking voltage temp. range pkg. si91872dmp-12-t1 si91872dmp-12-e3 7212 1.2 si91872dmp-18-t1 si91872dmp-18-e3 7218 1.8 si91872dmp-25-t1 si91872dmp-25-e3 7225 2.5 SI91872DMP-26-T1 si91872dmp-26-e3 7226 2.6 40 to 85 c mlp33 5 si91872dmp-28-t1 si91872dmp-28-e3 7228 2.8 ? 40 to 85 c mlp33-5 si91872dmp-30-t1 si91872dmp-30-e3 7230 3.0 si91872dmp-33-t1 si91872dmp-33-e3 7233 3.3 si91872dmp-50-t1 si91872dmp-50-e3 7250 5.0
si91872 vishay siliconix document number: 72013 s-51147?rev. f, 20-jun-05 www.vishay.com 5 typical characteristics (internally regulated, 25 c unless noted) ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 ? 0.0 0.2 0.4 ? 40 ? 15 10 35 60 85 normalized v out vs. t emperature ambient temperature ( c) (%) v out 0 50 100 150 200 250 300 234567 no load gnd pin current vs. input voltage ( i gnd a) input voltage (v) i out = 0 ma i out = 150 ma i out = 75 ma ? 40 c 85 c 50 75 100 125 150 0 50 100 150 200 250 300 gnd current vs. load current ( i gnd a) load current (ma) 600 625 650 675 700 725 750 ? 40 ? 15 10 35 60 85 output short circuit current vs. t emperature 85 c (ma) i sc ambienttemperature ( c) 25 c ? 80 ? 60 ? 40 ? 20 0 10 100 1000 10000 100000 1000000 power supply rejection frequency (hz) gain (db) c in = 1 f c out = 1 f i load = 150 ma v out = 3.0 v ? 0.75 ? 0.60 ? 0.45 ? 0.30 ? 0.15 0.00 0.15 0.30 0 50 100 150 200 250 300 normalized output voltage vs. load current output voltage (%) load current (ma) v out = 2.6 v v in = v out(nom) + 1 v v out = 3.0 v v in = 4.0 v v in = v out(nom) + 1 v 25 c ? 40 c i out = 300 ma
si91872 vishay siliconix www.vishay.com 6 document number: 72013 s-51147?rev. f, 20-jun-05 typical characteristics (internally regulated, 25 c unless noted) 0 50 100 150 200 250 300 350 0 60 120 180 240 300 dropout v oltage vs. load current i load (ma) (mv) v drop 0 50 100 150 200 250 300 350 ? 50 ? 25 0 25 50 75 100 125 150 dropout v oltage vs. t emperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0123456 v in ? v out transfer characteristic v in (v) (v) v out junction temperature ( c) 0 50 100 150 200 250 300 350 400 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 dropout voltage vs. v out dropout voltage (mv) v out (mv) v drop i out = 0 ma i out = 150 ma i out = 10 ma i out = 75 ma v out = 3.0 v v out = 3.0 v v out = 3.0 v i out = 10 ma i out = 75 ma i out = 150 ma i out = 300 ma i out = 300 ma
si91872 vishay siliconix document number: 72013 s-51147?rev. f, 20-jun-05 www.vishay.com 7 typical waveforms load t ransient response-1 i load 100 ma/div v out 10 mv/div v out = 3.0 v c out = 1 f i load = 1 to 150 ma t rise = 2 sec load t ransient response-2 v out = 3.0 v c out = 1 f i load = 150 to 1 ma t fall = 2 sec 20 s/div i load 100 ma/div v out 10 mv/div linetransient response-1 v out 10 mv/div v in 2 v/div v instep = 4 to 5 v v out = 3 v c out = 1 f c in = 1 f i load = 150 ma t rise = 5 sec 20 s/div linetransient respons-2 v instep = 5 to 4 v v out = 3 v c out = 1 f c in = 1 f i load = 150 ma t fall = 5 sec 20 s/div 20 s/div v out 10 mv/div v in 2 v/div
si91872 vishay siliconix www.vishay.com 8 document number: 72013 s-51147?rev. f, 20-jun-05 typical waveforms output noise v out 200 v/div noise spectrum 4 ms/div 10 hz v in = 4 v v out = 3 v i out = 150 ma bw = 10 hz to 100 khz 10 0.01 1 mhz v in = 4 v v out = 3 v i load = 150 ma v hz output spectral noise density functional block diagram si91872 v in reference ? + thermal sensor shutdown control gnd error v out reverse polarity protection current limit sd
si91872 vishay siliconix document number: 72013 s-51147?rev. f, 20-jun-05 www.vishay.com 9 detailed description the si91872 is a low-noise, low drop-out and low quiescent current linear voltage regulator, packaged in a small footprint mlp33-5 package. the si91872 can supply loads up to 300 ma. as shown in the block diagram, the circuit consists of a bandgap reference, error amplifier, p-channel pass transistor and feedback resistor string. additional blocks, not shown in the block diagram, include a precise current limiter, reverse battery and current protection, and thermal sensor. thermal overload protection the thermal overload protection limits the total power dissipation and protects the device from being damaged. when the junction temperature exceeds 150 c, the device turns the p-channel pass transistor off. reverse battery protection the si91872 has a battery reverse protection circuitry that disconnects the internal circuitry when v in drops below the gnd voltage. there is no current drawn in such an event. when the sd pin is hardwired to v in , the user must connect the sd pin to v in via a 100-k resistor if reverse battery protection is desired. hardwiring the sd pin directly to the v in pin is allowed when reverse battery protection is not desired. error error is an open drain output that goes low when v out is less than 4% of its normal value. to obtain a logic level output, connect a pull-up resister from error to v out or any other voltage equal to or less than v in . error pin is high impedance (off) when sd pin is low. auto-discharge v out has an internal 100- (typ.) discharge path to ground when sd pin is low for the si91872. stability the circuit is stable with only a small output capacitor equal to 6 nf/ma (= 2 f @ 300 ma). since the bandwidth of the error amplifier is around 1 ? 3 mhz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150-ma load current, an esr <0.2 is necessary. parasitic inductance of about 10 nh can be tolerated. safe operating area the ability of the si91872 to supply current is ultimately dependent on the junction temperature of the pass device. junction temperature is in turn dependent on power dissipation in the pass device, the thermal resistance of the package and the circuit board, and the ambient temperature. the power dissipation is defined as p d = (v in ? v out ) * i out . junction temperature is defined as t j = t a + ((p d * (r jc + r ca )). to calculate the limits of performance, these equations must be rewritten. allowable power dissipation is calculated using the equation p d = (t j ? t a )/ (r jc + r ca ) while allowable output current is calculated using the equation i out = (t j ? t a )/ (r jc + r ca ) * (v in ? v out ). ratings of the si91872 that must be observed are t jmax = 125 c, t amax = 85 c, (v in ? v out ) max = 5.3 v, r jc = 8 c/w. the value of r ca is dependent on the pc board used. the value of r ca for the board used in device characterization is approximately 46 c/w. figure 1 shows the performance limits graphically for the si91872 mounted on the circuit board used for thermal characterization. 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0123456 figure 1. safe operating area (a) i out v in ? v out (v) (v in ? v out ) max = 5.3 v t a = 50 c t a = 85 c t a = 70 c vishay siliconix maintains worldw ide manufacturing c apability. pr oducts may be manufactured at on e of several qualified locati ons. reliability data for silicon technology and package reliability repr esent a composite of all qualified locations. for re lated documents such as package/tape drawings, par t marking, and reliability data, see http://www.vishay.com/ppg?72013 .
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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